RiscV

Quick introduction to the RISC-V Vector spec. I thought some people might find this useful if they're trying to learn what SEW, ELEN, VLMAX, LMUL etc. mean.

The RISC-V vector C intrinsics provide users interfaces in the C language level to directly leverage the RISC-V “V” extension (RISC-V “V” Vector Extension, n.d.) (also abbreviated as “RVV”), with assistance from the compiler in handling instruction scheduling and register allocation. The intrinsics also aim to free users from responsibility of maintaining the correct configuration settings for the vector instruction executions. This document uses the term “RVV” as an abbreviation for the RISC-V “V” extension. This document uses the term “the RVV specification” to indicate the RISC-V “V” extension specification.

Earlier this month Canonical announced Ubuntu Linux support for the Orange Pi RV2 as a low-cost RISC-V developer board. The Orange Pi RV2 with eight RISC-V cores and 8GB of RAM costs just around $64 USD. The price point and specs were interesting that I ordered one and have been running performance benchmarks on it since for seeing how capable this is as finally an interesting, low-cost and readily available RISC-V board.

direct YT link: https://www.youtube.com/watch?v=9s8hPmCZ0mk

The European Chips Act has set ambitious goals and its implementation is a significant pan-european effort. From an academic perspective, last year we published an open letter emphasizing the critical importance of open-source EDA for academia in Europe. We were excited and grateful to see that this initiative triggered the definition of a European roadmap in this area, and a matching Chips JU call for project funding. We believe that the projects funded by this call will have a significant impact. Moreover, we already see rising interest from many EU stakeholders, with increasing investments into open-source chip design, especially in open source IP development (e.g. RISC-V cores), and open source EDA tools.

One additional critical barrier remains toward the end-goal of building real open-source chips, especially for prototyping and education: namely, streamlining the access to open source chip production facilities (foundries) is essential. Programs like ChipIgnite, Tiny Tapeout and IHP’s open source program have become “guiding stars” that demonstrate that everyone with a computer can build chips. We believe that having low-cost, regular and easy access to chip production is critical to create excitement and build up expertise, widening the pool of chip designers with tape-out experience: a true silicon democratization and a further de-mystification of chip design.

cross-posted from: https://lemmy.world/post/26909445

Crossposted from https://lemmy.ml/post/21673583

RISC-V International, the global standards organization, today announced that the RVA23 Profile is now ratified. RVA Profiles align implementations of RISC-V 64-bit application processors that will run rich operating systems (OS) stacks from standard binary OS distributions. RVA Profiles are essential to software portability across many hardware implementations and help to avoid vendor lock-in. The newly ratified RVA23 Profile is a major release for the RISC-V software ecosystem and will help accelerate widespread implementation among toolchains and operating systems.

Each Profile specifies which ISA features are mandatory or optional, providing a common target for software developers. Mandatory extensions can be assumed to be present, and optional extensions can be discovered at runtime and leveraged by optimized middleware, libraries, and applications.

Key Components of RVA23 Include:

• Vector Extension: The Vector extension accelerates math-intensive workloads, including AI/ML, cryptography, and compression / decompression. Vector extensions yield better performance in mobile and computing applications with RVA23 as the baseline requirement for the Android RISC-V ABI.
• Hypervisor Extension: The Hypervisor extension will enable virtualization for enterprise workloads in both on-premises server and cloud computing applications. This will accelerate the development of RISC-V-based enterprise hardware, operating systems, and software workloads. The Hypervisor extension will also provide better security for mobile applications by separating secure and non-secure components.